1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having an internal circuit responsive to an external signal for carrying out a predetermined operation and a semiconductor device formed on a semiconductor substrate.
2. Description of the Background Art
FIG. 6 is a block diagram showing a structure of a conventional dynamic random access memory (hereinafter referred to as DRAM). Referring to FIG. 6, this DRAM includes control signal input terminals 31, 32, 34 and 42, an address signal input terminal 33, a data signal input/output (I/O) terminal 41, power supply terminals 35 to 39, and a ground terminal 40. The DRAM further includes an RAS buffer 43, a CAS buffer 44, a WE buffer 45, an OE buffer 46, a clock generating circuit 47, an address buffer 48, a row decoder 49, a column decoder 50, a memory cell array 51, and a sense amplifier +I/O control circuit 52. The DRAM further includes a preamplifier 53, an output buffer 54, a data-in buffer 55, a write driver 56, a VPP circuit 57, a VDC circuit 58 for sense amplifier, and a VDC circuit 59 for column-related circuit.
Buffers 43 to 46 generates internal control signals in response to external control signals ext./RAS, ext./CAS, ext./WE and ext./OE applied through control signal input terminals 31, 32, 34 and 42, respectively. Clock generating circuit 47 selects a prescribed operation mode based on the respective internal control signals applied from buffers 43 to 46 to control the entire DRAM.
Address buffer 48 generates an internal address signal in response to an external address signal ext.Add. applied through address signal input terminal 33, and selectively applies the internal address signal to row decoder 49 and column decoder 50. Memory cell array 51 includes a plurality of memory cells MCs arranged in a matrix in row and column directions, a word line WL provided corresponding to each row, and a bit line pair BLP provided corresponding to each column.
Row decoder 49 selects any one word line WL from memory cell array 51 in response to the internal address signal applied from address buffer 48. A boosted potential VPP is applied to the selected word line WL, whereby a memory cell MC corresponding to that word line WL is activated. Column decoder 50 selects any one bit line pair BLP from memory cell array 51 in response to the internal address signal applied from address buffer 48. Sense amplifier +I/O control circuit 52 connects the bit line pair BLP selected by column decoder 50 to one end of a global signal I/O line pair GIO. More specifically, a memory cell MC located at an intersection of the word line WL selected by row decoder 49 and the bit line pair BLP selected by column decoder 50 is connected to one end of the global signal I/O line pair GIO.
The other end of the global signal I/O line pair GIO is connected to preamplifier 53 and write driver 56. In read operation, preamplifier 53 and output buffer 54 amplifies data read from the selected memory cell MC and outputs the resultant data to data signal I/O terminal 41. In write operation, data-in buffer 55 and write driver 56 applies data externally applied through data signal I/O terminal 41 to the selected memory cell MC through the global signal I/O line pair GIO.
An external power supply potential ext.VCC applied through power supply terminal 35 is applied to buffers 43 to 46 (shown as a portion B in the figure). VPP circuit 57 boosts an external power supply potential ext.VCC applied through power supply terminal 36 to produce a boosted potential VPP for word line WL. VDC circuit 58 down-converts an external power supply potential ext.VCC applied through power supply terminal 37 to produce an internal power supply potential int.VCC and applies the internal power supply potential int.VCC to sense amplifier +I/O control circuit 52. VDC circuit 59 down-converts an external power supply potential ext.VCC applied through power supply terminal 38 to produce an internal power supply potential int.VCC and applies the internal power supply potential int.VCC to the column-related circuit (shown as a portion A in the figure). An external power supply potential ext.VCC applied through power supply terminal 39 is applied to output buffer 54. An external ground potential ext.VSS applied through ground terminal 40 is applied to the entire DRAM.
FIG. 7 is a plan view showing a structure of a DRAM chip 60 integrated in a package, wherein illustration of some components is omitted.
In FIG. 7, the DRAM of FIG. 6 is formed at a surface of DRAM chip 60. A plurality of pads (only pads P1 to P8 are shown in the figure) are arranged in the middle of the surface of DRAM chip 60. Pads P1, P3 and P8 constitute power supply terminals 37, 39 and 36 of FIG. 6, respectively. Pads P5 and P6 constitute control signal input terminals 31 and 32 of FIG. 6, respectively. Pad 7 constitute power supply terminals 35 and 38 of FIG. 6.
A plurality of lead frames (only lead frames 61 to 65 are shown in the figure) are located above DRAM chip 60. Lead frame 61 includes a base portion 61a and a branch portion 61b branching away from a tip portion of base portion 61a. A base end portion of base portion 61a is connected to a pin of a package which is not shown, and the tip portion is connected to pads P1 and P2 through bonding wires 66. A tip portion of branch portion 61b is connected to pad P3 through a bonding wire 66. Base end portions of lead frames 62 to 65 are connected to pins of the package which is not shown, and tip portions thereof are connected to pads P5 to P8 by bonding wires 66, respectively. An external power supply potential ext.VCC and an external control signal are applied to the DRAM through lead frames 61 to 65, bonding wires 66 and pads P1 to P8.
A noise removing capacitor constituted by an n channel MOS transistor 70 is provided between an external power supply potential ext.VCC line and an external ground potential ext.VSS line of the DRAM, as shown in FIG. 8. The n channel MOS transistor 70 has its gate connected to the external power supply potential ext.VCC line, and its source and drain connected in common to the external ground potential ext.VSS line.
FIG. 9A is a fragmentary plan view showing a structure of a portion including n channel MOS transistor 70 in DRAM chip 60, and FIG. 9B is a cross sectional view taken along the line Y-Y' of FIG. 9A. Referring to FIGS. 9A and 9B, a gate electrode 73 is formed on a surface of a p type silicon substrate 71 of DRAM chip 60 with a gate oxide film 72 interposed therebetween. An n type source region 74 is formed on one side of gate electrode 73, and an n type drain region 75 is formed on the other side thereof, so that n channel MOS transistor 70 is formed.
An external ground potential ext.VSS line 76 is provided above the surface of silicon substrate 71 with an insulating layer 78 interposed therebetween, and an external power supply potential ext.VCC line 77 is further provided above external ground potential ext.VSS line 76 with insulating layer 78 therebetween. External ground potential ext.VSS line 76 is formed of a first aluminum interconnection layer (AR1), and external power supply potential ext.VCC line 77 is formed of a second aluminum interconnection layer (AR2). External power supply potential ext.VCC line 77 is connected to gate electrode 73 of n channel MOS transistor 70 through a contact hole 79, and external ground potential ext.VSS line 76 is connected to source region 74 and drain region 75 of n channel MOS transistor 70 through respective contact holes 80 and 81.
Since an external power supply potential ext.VCC is applied to gate electrode 73 of n channel MOS transistor 70 and an external ground potential ext.VSS is applied to source region 74 and drain region 75 thereof, a channel is formed in a region under gate oxide film 72 at the surface of p type silicon substrate 71, and a capacitor is formed between gate electrode 73 and the channel.
FIG. 10 is a circuit diagram showing a structure of output buffer 54 of FIG. 6. Referring to FIG. 10, this output buffer 54 includes two inverters 82 and 83 and an output circuit 84. Inverter 82 includes a p channel MOS transistor 85 and an n channel MOS transistor 86 which are connected in series between an internal power supply potential int.VCC line and an external ground potential ext.VSS line, and produces an inverted signal /Nd of an internal data signal Nd output from preamplifier 53. Inverter 83 includes a p channel MOS transistor 87 and an n channel MOS transistor 88 which are connected in series between the internal power supply potential ext.VCC line and the external ground potential ext.VSS line, and produces an inverted signal Nd of an internal data signal /Nd output from preamplifier 53.
Output circuit 84 includes two n channel MOS transistors 89 and 90. The n channel MOS transistor 89 is connected between an external power supply potential ext. VCC line and data signal I/O terminal 41, and receives an output of inverter 82 at its gate. The n channel MOS transistor 90 is connected between data signal I/O terminal 41 and the external ground potential ext.VSS line, and receives an output of inverter 83 at its gate.
When the internal data signal Nd is at an "H" level, inverters 82 and 83 output signals at an "L" level and an "H" level, respectively, and n channel MOS transistor 89 is rendered non-conductive and n channel MOS transistor 90 is rendered conductive, so that data signal I/O terminal 41 falls to an "L" level. Furthermore, when the internal data signal Nd is at an "L" level, inverters 82 and 83 output signals at an "H" level and an "L" level, respectively, and n channel MOS transistor 89 is rendered conductive and n channel MOS transistor 90 is rendered non-conductive, so that data signal I/O terminal 41 attains an "H" level.
FIG. 11 is a fragmentary plan view showing a structure of a portion including output circuit 84 in DRAM chip 60. Referring to FIG. 11, a plurality (three in the figure) of output circuits 84 are provided at the surface of DRAM chip 60. An external ground potential ext.VSS line 91 and an external power supply potential ext.VCC line 92 are located above the plurality of output circuits 84. The external ground potential ext.VSS line is connected to each output circuit 84 through a contact hole 93. The external power supply potential ext.VCC line is connected to each output circuit 84 through a contact hole 94. External ground potential ext.VSS line 91 has its one end connected to a pad P0, which in turn receives an external ground potential ext.VSS. External power supply potential ext.VCC line 92 extends under external ground potential ext.VSS line 91 and then is connected to a pad P3.
FIG. 12A is an enlarged view showing a structure of a cross under portion (shown as a portion C in the figure) of FIG. 11, and FIG. 12B is a cross sectional view taken along the line Z-Z' of FIG. 12A. External ground potential ext.VSS line 91 and external power supply potential ext.VCC line 92 are formed of a second aluminum interconnection layer (AR2). A connection electrode 95 having a width larger than that of external ground potential ext.VSS line 91 is formed of a first aluminum interconnection layer (AR1) under external ground potential ext.VSS line 91, and both ends of connection electrode 95 are connected to external power supply potential ext.VCC line 92 through respective contact holes 96.
FIG. 13 is a circuit diagram showing a structure of VDC circuit 59. Referring to FIG. 13, this VDC circuit 59 includes a p channel MOS transistor 97 and an operational amplifier 98. The p channel MOS transistor 97 is connected between an external power supply potential ext.VCC line and an internal power supply potential int.VCC line, and receives an output of operational amplifier 98 at its gate. A non-inverting input terminal of operational amplifier 98 receives a reference potential VREF (VREF&lt;VCC), and an inverting input terminal thereof is connected to the internal power supply potential int.VCC line. Operational amplifier 98 controls a gate potential of p channel MOS transistor 97 so that the internal power supply potential int.VCC matches the reference potential VREF.
FIG. 14 is a fragmentary plan view showing a structure of a portion including VDC circuit 59 in DRAM chip 60.
Referring to FIG. 14, VDC circuit 59 is provided at the surface of DRAM chip 60. An external power supply potential ext.VCC line 100, an external ground potential ext.VSS line 101 and an internal power supply potential int.VCC line 102 are located above VDC circuit 59. External power supply potential ext.VCC line 100, external ground potential ext.VSS line 101 and internal power supply potential int.VCC line 102 are connected to VDC circuit 59 through respective contact holes 103, 104 and 105. External power supply potential ext.VCC line 100 has its one end connected to a pad P7. External power supply potential ext.VCC line 100 and internal power supply potential int.VCC line 102 intersect each other. External ground potential ext.VSS line 101 extends under lines 100 and 102 and then is connected to a pad P0.
Since the conventional DRAM has been structured as such, there have been the following problems.
First, when the internal data signals Nd and /Nd switch in FIG. 10, both n channel MOS transistors 89 and 90 in output circuit 84 are rendered conductive and a potential at pad P3 is reduced temporarily. This temporary reduction in potential is transmitted as power supply noise from pad P3 through lead frame 61 to other pads P1 and P2 of FIG. 7, causing malfunction of VDC circuit 58 or the like.
Although it is possible to respectively provide lead frames 110 and 111 to pads P1 and P2 and pad P3 as shown in FIG. 15 in order to prevent transmission of power supply noise from pad P3 to pads P1 and P2, this causes increase in the number of pins in the package.
Second, since VDC circuit 59 and buffers 43 to 46 receive an external power supply potential ext.VCC from the same pad P7, buffers 43 to 46 malfunction due to power supply noise of VDC circuit 59, and on the contrary, VDC circuit 59 malfunctions due to power supply noise of buffers 43 to 46.
Third, the external power supply potential ext.VCC line is formed only of the second aluminum interconnection layer (AR2) in FIG. 9, resulting in high interconnection resistance at the external power supply potential ext.VCC line.
Fourth, there exist such cross under portions C and D as shown in FIGS. 11 and 14 in the power supply lines, resulting in high interconnection resistance at the power supply lines.